library ieee;
use ieee.std_logic_1164.all;

-- This arbitrary state machine is probably not very useful in reality, but demonstrates 

entity xmt_emulator is
    port (clock               			: in  std_logic;
          reset               			: in  std_logic;
          XMT_to_FWD_spaceavailable		: out std_logic_vector(10 downto 0);
		  XMT_to_FWD_ACK				: out std_logic;
	      FWD_to_XMT_DATA				: in  std_logic_vector(7 downto 0);
	      FWD_to_XMT_ACK				: in  std_logic;
	      FWD_to_XMT_DONE				: in  std_logic;
	      FWD_to_XMT_LENGTH				: in  std_logic_vector(11 downto 0)
    );
end xmt_emulator;

architecture behavior of xmt_emulator is

type   state_type is (wait_state, ack_state);
signal my_state_reg, my_state_next: state_type:= wait_state;


component ctrl_ff is
	port
	(
		aclr		: in  std_logic;
		clock		: in  std_logic;
		data		: in  std_logic;
		enable		: in  std_logic;
		q			: out std_logic
	);
end component;

begin

-- Update state on rising edges or a reset
process(clock, reset)
	begin
		if(reset ='1') then 
		  my_state_reg <= wait_state;
		elsif(clock'event and clock='1') then
			my_state_reg<=my_state_next;
		end if;
	end process;

process(my_state_reg, FWD_to_XMT_ACK) 
	begin
		if FWD_TO_XMT_ACK='1' then
			my_state_next <= ack_state;
		else
			my_state_next <= wait_state;
		end if;
	end process;
	
process (my_state_reg)  -- Moore output logic
	begin
		case my_state_reg is
			when wait_state => XMT_to_FWD_ACK <= '0'; 
			when ack_state => XMT_to_FWD_ACK <= '1'; 
		end case;
	end process;

XMT_to_FWD_spaceavailable <= "01010101010";

end behavior;